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[Other resource] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5356 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[Other] UnsignMulti

Description: ALTERA上DE2平台，verilog描述，无符号乘法器，在数码管显示结果。-ALTERA on DE2 platform, verilog description unsigned multiplier, the result will be displayed in the digital pipe.
Platform: | Size: 878592 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog

Description: 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water lamp experiment, digital pipe display experimentation, etc
Platform: | Size: 10240 | Author: 星光依旧 | Hits:

[VHDL-FPGA-Verilog] P8

Description: PIPE LINE VERILOG PROJECT
Platform: | Size: 121856 | Author: rahim | Hits:

[VHDL-FPGA-Verilog] SEG

Description: 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
Platform: | Size: 1024 | Author: 金纯 | Hits:

[VHDL-FPGA-Verilog] Fpga-based-ADC-sampling-voltage-

Description: 基于fpga的ADC采样电压用，显示在数码管上。verilog语言。-Fpga-based ADC sampling voltage used, displayed on the digital pipe. verilog language.
Platform: | Size: 2267136 | Author: 祖儿 | Hits:

[Other] miaobiao

Description: 一个精确的秒表，显示在数码管上。对于初学者使用verilog有很大的帮助，同时注释很详细。-An accurate stopwatch displayed on the digital pipe. For beginners verilog a great help, and very detailed notes.
Platform: | Size: 875520 | Author: 许昌 | Hits:

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